About

I am a Ph.D. student in Computer Science at the University of Maryland, College Park. My research lies at the intersection of machine learning and systems, with a focus on resilient and efficient IoT-driven smart environments. I am particularly interested in lightweight Transformer-based methods for real-time sensing reliability, fault detection, and diagnosis at the edge.

Research Interests

  • Machine Learning for IoT Reliability

    Self-supervised and context-aware ML methods for fault detection in smart-home systems

  • Transformer Models for Multivariate Time-Series Data

    Lightweight Transformer architectures for modeling spatiotemporal correlations and abnormal behavior in heterogeneous IoT streams

  • Edge AI Systems

    Real-time ML inference and low-overhead deployment on resource-constrained IoT gateways and embedded devices

  • Efficient ML Computing

    HW/SW co-design, parallel computing, and FPGA-based acceleration for ML workloads

Publications

  1. Tureis: Transformer-based Unified Resilience for IoT Devices in Smart Homes
    A. Borhani, V. Andalibi, B. Asgari
    Submitted to the ACM/IEEE International Conference on Embedded Artificial Intelligence and Sensing Systems (SenSys), 2027.
    arXiv Under review
  2. ThingsDND: IoT Device Failure Detection and Diagnosis for Multi-User Smart Homes
    A. Borhani, H. R. Zarandi
    18th European Dependable Computing Conference (EDCC), pp. 113–116, 2022.
    Paper Slides
  3. FAST: FPGA Acceleration of Neural Networks Training
    A. Borhani, M. H. Goharinejad, H. R. Zarandi
    12th International Conference on Computer and Knowledge Engineering (ICCKE), pp. 492–497, 2022.
    Paper Slides Recording

Selected Projects

  1. Tureis: Self-Supervised Resilience for Smart-Home IoT Devices

    Lightweight Transformer-based framework for localizing simultaneous sensor failures in heterogeneous smart-home IoT deployments.

    • ML for IoT Reliability
    • Transformer Time-Series Modeling
    • Edge AI Systems
  2. ThingsDND: Context-Aware Failure Detection and Diagnosis

    Automatic context-aware framework for detecting and diagnosing sensor failures in multi-user smart homes.

    • ML for IoT Reliability
    • BiLSTM Time-Series Modeling
    • Smart-Home Sensing
  3. FAST: FPGA Acceleration of Neural Network Training

    Low-precision FPGA framework for accelerating neural-network training on resource-constrained embedded platforms.

    • Efficient ML Computing
    • Fixed-Point FPGA Acceleration
    • HW/SW Co-Design

Additional Projects

7 projects

  1. FPGA-Oriented Matrix Computation and Sparse Storage Analysis

    Developed Python-based simulation and analysis tools for FPGA-style matrix-computation accelerators. The project involved implementing cycle-accurate simulators for output-stationary and weight-stationary systolic-array matrix multiplication, modeling token movement, MAC activity, partial-sum propagation, latency, and array utilization. Also analyzed CSR, COO, BCSR, and FPGA-friendly LIL-style sparse layouts in terms of metadata overhead, storage efficiency, decompression cost, BRAM access patterns, and parallel-read feasibility.

  2. Comparative Study of Parallel Programming Frameworks

    Evaluated shared-memory and message-passing parallel programming frameworks on the Zaratan HPC cluster, comparing OpenMP, Intel TBB, C++ Parallel STL, OpenMPI, and Intel MPI across NAS Parallel Benchmarks and SPEC HPC workloads. The project involved porting selected benchmark kernels, running scalability experiments across thread counts and MPI-rank configurations, and using Intel VTune and HPCToolkit to analyze performance bottlenecks related to communication overhead, synchronization cost, NUMA effects, memory behavior, load balance, and framework-level runtime overhead.

  3. RTL-to-GDSII Digital Design Flow

    Implemented a complete RTL-to-layout flow for a 13K-cell arithmetic core using Synopsys Design Compiler and Cadence Encounter SoC. Starting from Verilog RTL, the design was synthesized with a TSMC 180nm standard-cell library, evaluated through area, timing, and power reports, and optimized under both minimum-area and target-frequency constraints. The synthesized netlist and constraints were then used for floorplanning, power routing, placement, clock routing, signal routing, filler-cell insertion, timing verification, DRC/connectivity checks, and final GDS generation.

  4. SRAM vs. STT-RAM Cache Energy Modeling

    Developed a simulation-based evaluation flow for comparing SRAM and STT-RAM L2 cache designs using gem5 and NVSim. PARSEC workloads were executed in gem5 full-system simulation with a modeled L1/L2 cache hierarchy to collect workload-specific L2 read/write access statistics. These access profiles were then combined with NVSim memory models to estimate read energy, write energy, and leakage power, enabling a workload-aware comparison of cache energy behavior across memory technologies.

  5. FPGA-Based Hardware/Software Co-Design and Validation

    Evaluated the Tiny Tate Bilinear Pairing arithmetic core through an FPGA-based hardware/software co-design flow. The project involved analyzing a hierarchical Verilog design composed of datapath, RAM, ROM, control, and processing modules; synthesizing the design with Xilinx ISE for a Spartan-3 FPGA; and validating its behavior using ISim simulation. Functional correctness was verified through Verilog testbenches that wrote input operands into RAM, triggered the computation, read back the generated outputs, and compared them against expected results.

  6. Simulated Annealing for VLSI Standard-Cell Placement

    Implemented a simulated-annealing-based placement algorithm for standard-cell VLSI physical design by extending a C/C++ placement framework and its internal design database. The project optimized cell locations using wirelength-aware cost evaluation while preserving row-based, overlap-free layout constraints. The implementation included benchmark parsing, cell-move generation, cost estimation based on half-perimeter wirelength, iterative placement refinement, and graphical validation of the final layout.

  7. Embedded Sensing, Actuation, and Rapid Prototyping

    Designed and implemented a series of ESP32-based embedded systems integrating sensor input, actuator control, wireless communication, and custom-fabricated mechanical components, including Morse-code LED signaling, a light-sensor-based audio feedback game, a 3D-printed ultrasonic radar platform with servo-driven scanning, an IMU-based LED tilt indicator, a remotely controlled bridge-crossing robot, and a multi-node wireless musical robotics system with real-time beat synchronization, per-node pitch control, buzzer-based audio output, LED feedback, custom 3D-printed enclosures, and laser-cut structural components.

Experience

  1. Research Assistant

    • Computer Architecture and Systems Lab (CASL) University of Maryland, College Park

      Conducting research on resilient IoT sensing systems, with a focus on self-supervised Transformer models for smart-home sensor failure detection, localization, and edge-efficient inference.

    • Embedded Systems Research Laboratory (ESRLab) Sharif University of Technology

      Studied energy-efficient and aging-aware memory hierarchies for multicore systems. Developed a simulation-based evaluation flow using gem5 and NVSim to compare SRAM and STT-RAM cache energy behavior under PARSEC workloads.

    • Design and Analysis of Dependable Systems (DADS) Laboratory Amirkabir University of Technology

      Worked on dependable IoT systems and efficient ML hardware. Contributed to context-aware sensor failure detection in smart homes and FPGA-based acceleration of neural-network training.

  2. Research Intern

    Demo

    Embedded Systems Research Laboratory (ESRLab) Sharif University of Technology

    Developed an Arduino-based IoT environmental monitoring system with Wi-Fi-enabled distributed sensor nodes, and implemented fault-tolerant redundancy mechanisms, including Triple Modular Redundancy (TMR) and hot standby, to improve system reliability while reducing energy overhead.

  1. Teaching Assistant

    • Algorithms University of Maryland, College Park

      Graded homework and exams, held office hours, and proctored exams.

    • Reliable Systems Design · Graduate course Amirkabir University of Technology

      Designed and graded graduate homework and projects.

    • VLSI Design Algorithms · Graduate course Amirkabir University of Technology

      Designed and graded graduate homework and projects.

    • Design of Algorithms Shahed University

      Led instructional sessions and designed and graded homework and exams.

  2. Laboratory Instructor

    • Operating Systems Laboratory Amirkabir University of Technology

      Instructed students in Linux process management, CPU scheduling, multithreading, synchronization, and inter-process communication.

    • Logic Circuits Laboratory Amirkabir University of Technology

      Instructed students in combinational and sequential logic design, Verilog HDL programming, simulation, and FPGA implementation.

    • Computer Architecture Laboratory Amirkabir University of Technology

      Instructed students in datapath and control-unit design, VHDL-based processor implementation, simulation, and FPGA prototyping.

  1. Embedded Systems Developer

    LUXIN Smart Home Tehran, Iran

    Developed embedded software features for smart-home systems, including air-conditioner control, smart blinds, and current-consumption monitoring for connected devices.

Contact

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